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rev. 1.0 12/09 copyright ? 2009 by silicon laboratories si4704/05-c40 n ot r ec omm ende d for new d esig ns si4704/05-c40 b roadcast fm r adio r eceiver for c onsumer e lectronics features applications description the si4704/05 integrates all functions required for an advanced broadcast fm radio receiver, from antenna i nput to stereo audio output. functional block diagram ? worldwide fm band support (64?108 mhz) ? integrated antenna support ? en55020 compliant ? excellent real-world performance ? freq synthesizer with integrated vco ? advanced fm seek tuning ? automatic frequency control (afc) ? automatic gain control (agc) ? digital fm stereo decoder ? minimal bom ? programmable de-emphasis ? programmable reference clock ? volume control ? adjustable soft mute control ? rds/rbds processor (si4705) ? optional digital audio out (si4705) ? 2-wire and 3-wire control interface ? integrated ldo regulator ? signal quality measurements ? 2.7 to 5.5 v supply voltage ? 3x3 mm 20-pin qfn package ? rohs compliant ? table and portable radios ? stereos ? mini/micro systems ? cd/dvd players ? boom boxes ? modules ? clock radios ? mini hifi ? entertainment systems adc adc si4704/05 dsp dac dac rout lout afc digital interface (si4705) gpo rfgnd lna fmi agc pga rclk reg vdd 2.7?5.5 v fm antenna xtal osc lpi 32.768 khz 0/90 dout dclk dfs vio 1.85-3.6 v sclk sdio control interface sen rssi rst rds (si4705) this product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,27 2,375; 7,321,324; 7,355,476; 7,42 6,376; 7,471,940; 7,339,503; 7,339,504. ordering information: see page 28. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio dout lout rout gnd rst nc lpi rclk sdio vdd fmi rfgnd gpo3/dclk nc gpo1 dfs sclk sen si4704/05-gm (top view) free datasheet http:///
si4704/05-c40 2 rev. 1.0 free datasheet http:///
si4704/05-c40 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.2. application schematics and operat ing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. fm receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4. digital audio interface (si4705 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5. stereo audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6. de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 4.7. stereo dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8. soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.9. rds/rbds processor (si4705 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.10. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.11. seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.12. reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.13. control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 4.14. gpo outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.15. reset, powerup, and powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.16. programming wi th commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. commands and propertie s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. pin descriptions: si4704/ 05-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1. si4704 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2. si4705 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9. package outline: si 4704/05-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10. pcb land pattern: si4704/05-c 40-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 free datasheet http:///
si4704/05-c40 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage v dd 2.7 ? 5.5 v interface supply voltage v io 1.85 ? 3.6 v digital power supply powerup rise time v drise 10 ? ? s interface power supply powerup rise time v iorise 10 ? ? s ambient temperature t a ?20 25 85 ? c note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v dd = 3.3 v and 25 ? c unless otherwise stated. parameters are tested in production unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit supply voltage v dd ?0.5 to 5.8 v interface supply voltage v io ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v io + 0.3) v operating temperature t op ?40 to 95 ? c storage temperature t stg ?55 to 150 ? c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data shee t. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si4704/05 devices are high-performanc e rf integrated circuits with certain pins having an esd rating of < 2 kv hbm. handling and assembly of these devices shoul d be done only at esd-protected workstations. 3. for input pins sclk, sen, sdio, rst, rcl k, dclk, dfs, gpo1, gpo2, and gpo3. 4. at rf input pin, fmi. free datasheet http:///
si4704/05-c40 rev. 1.0 5 table 3. dc characteristics (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit fm receiver to line output supply current 1 i fm ?19.222ma supply current 2 i fm low snr level ? 19.9 23 ma rds supply current 1 i fm ?19.223ma supplies and interface interface supply current i io ?320600a v dd powerdown current i ddpd ?1020 a v io powerdown current i iopd sclk, rclk inactive ? 1 10 a high level input voltage 3 v ih 0.7 x v io ?v io +0.3 v low level input voltage 3 v il ?0.3 ? 0.3 x v io v high level input current 3 i ih v in =v io =3.6v ?10 ? 10 a low level input current 3 i il v in =0v, v io =3.6v ?10 ? 10 a high level output voltage 4 v oh i out =500a 0.8xv io ??v low level output voltage 4 v ol i out = ?500 a ? ? 0.2 x v io v notes: 1. guaranteed by characterization. 2. lna is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 3. for input pins sclk, sen, sdio, rst, rcl k, dclk, dfs, gpo1, gpo2, and gpo3. 4. for output pins sdio, dout, gpo1, gpo2, and gpo3. free datasheet http:///
si4704/05-c40 6 rev. 1.0 figure 1. reset timing parameters for busmode select table 4. reset timing characteristics 1,2,3 (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol min typ max unit rst pulse width and gpo1, gpo2/int setup to rst ? ? t srst 100 ? ? s gpo1, gpo2/int hold from rst ? t hrst 30 ? ? ns important notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 2-wire mode, the user must ensure t hat sclk is high during the rising edge of rst , and stays high until after the first start condition. 3. when selecting 3-wire or spi modes, the user must ensure th at a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 4. if gpo1 and gpo2 are actively driven by the user, then minimum t srst is only 30 ns. if gpo1 or gpo2 is high impedance, then minimum t srst is 100 s to provide time for on-chip 1 m ? devices (active while rst is low) to pull gpo1 high and gpo2 low. 70% 30% gpo1 70% 30% gpo2/ int 70% 30% t srst rst t hrst free datasheet http:///
si4704/05-c40 rev. 1.0 7 table 5. 2-wire control interface characteristics 1,2,3 (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f scl 0?400khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 ? ? s sclk input to sdio ? setup (start) t su:sta 0.6 ? ? s sclk input to sdio ? hold (start) t hd:sta 0.6 ? ? s sdio input to sclk ? setup t su:dat 100 ? ? ns sdio input to sclk ? hold 4, 5 t hd:dat 0?900ns sclk input to sdio ? setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out ?250ns sdio input, sclk rise/fall time t f:in t r:in ?300ns sclk, sdio capacitive loading c b ??50pf input filter pu lse suppression t sp ? ? 50 ns notes: 1. when v io = 0 v, sclk and sdio are low impedance. 2. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst , and stays high until after the first start condition. 4. the si4704/05 delays sdio by a minimum of 300 ns from the v ih threshold of sclk to comply with the minimum t hd:dat specification. 5. the maximum t hd:dat has only to be met when f scl = 400 khz. at frequencies below 400 khz, t hd:dat may be violated as long as all other timing parameters are met. 20 0.1 c b 1pf ---------- - + 20 0.1 c b 1pf ---------- - + free datasheet http:///
si4704/05-c40 8 rev. 1.0 figure 2. 2-wire control interface read and write timing parameters figure 3. 2-wire control interface read and write timing diagram sclk 70% 30% sdio 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out sclk sdio start stop address + r/w ack data ack data ack a6-a0, r/w d7-d0 d7-d0 free datasheet http:///
si4704/05-c40 rev. 1.0 9 figure 4. 3-wire control interface write timing parameters figure 5. 3-wire control interface read timing parameters table 6. 3-wire control interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk ?? setup t s 20 ? ? ns sdio input to sclk ?? hold t hsdio 10 ? ? ns sen input to sclk ? ? hold t hsen 10 ? ? ns sclk ?? to sdio output valid t cdv read 2 ? 25 ns sclk ?? to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r , t f ? ? 10 ns sclk 70% 30% sen 70% 30% sdio a7 a0 70% 30% t s t s t hsdio t hsen a6-a5, r/w, a4-a1 address in data in d15 d14-d1 d0 t high t low t r t f ? cycle bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio t cdv t cdz address in data out a7 a0 a6-a5, r/w, a4-a1 d15 d14-d1 d0 t s t s t hsen free datasheet http:///
si4704/05-c40 10 rev. 1.0 figure 6. spi control interface write timing parameters figure 7. spi control interface read timing parameters table 7. spi control interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk ?? setup t s 15 ? ? ns sdio input to sclk ?? hold t hsdio 10 ? ? ns sen input to sclk ? ? hold t hsen 5??ns sclk ? ? to sdio output valid t cdv read 2 ? 25 ns sclk ? ? to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r t f ? ? 10 ns note: when selecting spi mode, the user must ensure that a rising edge of sclk d oes not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio c7 c0 70% 30% t s c6 ?c1 control byte in 8 data bytes in d7 d6 ?d1 d0 t s t hsdio t high t low t hsen t f t r bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio control byte in c7 c0 c6 ?c1 t s t hsen t s t cdz t cdv 16 data bytes out (sdio or gpo1) d7 d6 ?d1 d0 free datasheet http:///
si4704/05-c40 rev. 1.0 11 figure 8. digital audio interface timing parameters, i 2 s mode table 8. digital audio interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit dclk cycle time t dct 26 ? 1000 ns dclk pulse width high t dch 10 ? ? ns dclk pulse width low t dcl 10 ? ? ns dfs set-up time to dclk rising edge t su:dfs 5?? ns dfs hold time from dclk rising edge t hd:dfs 5?? ns dout propagation delay from dclk falling edge t pd:dout 0?12ns dclk dfs t dct t pd:out t su:dfs t hd:dfs dout t dch t dcl free datasheet http:///
si4704/05-c40 12 rev. 1.0 table 9. fm receiver characteristics 1,2 (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 76 ? 108 mhz sensitivity with headphone network 3,4,5 (s+n)/n = 26 db ? 2.2 3.5 v emf sensitivity with 50 ? network 3,4,5,6 (s+n)/n = 26 db ? 1.1 ? v emf rds sensitivity 6 ? f = 2 khz, rds bler < 5% ?15?v emf lpi sensitivity 6 ? 3.5 ? v emf lna input resistance 6,7 345 k ? lna input capacitance 6,7 456 pf input ip3 6,8 100 105 ? dbv emf am suppression 3,4,6,7 m = 0.3 40 50 ? db adjacent channel selectivity 200 khz 35 50 ? db alternate channel selectivity 400 khz 60 70 ? db spurious response rejection 6 in-band 35 ? ? db audio output voltage 3,4,7 72 80 90 mv rms audio output l/r imbalance 3,7,9 ?? 1 db audio frequency response low 6 ?3 db ? ? 30 hz audio frequency response high 6 ?3 db 15 ? ? khz audio stereo separation 7,9 32 42 ? db audio mono s/n 3,4,5,7,10 55 63 ? db audio stereo s/n 4,5,6,7,10,11 ?58? db blocking sensitivity 3,6,12,13 ? f = 400 khz ? 32 ? dbv ? f = 4 mhz ? 38 ? dbv notes: 1. additional testing information is available in applicati on note, ?an388: si470x/1x/2x/3 x/4x evaluation board test procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines? silicon laboratories will evaluate schematics and layo uts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. guaranteed by characterization. 7. v emf =1 mv. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 9. ? f = 75 khz. 10. at l out and r out pins. 11. analog audio output mode. 12. blocker amplitude = 100 dbv 13. sensitivity measured at (s+n)/n = 26 db. 14. at temperature 25c. free datasheet http:///
si4704/05-c40 rev. 1.0 13 intermod sensitivity 3,6,12,13 ? f = 400 khz, 800 khz ? 40 ? dbv ? f = 4 mhz, 8 mhz ? 35 ? dbv audio thd 3,7,9 ?0.10.5 % de-emphasis time constant 6 fm_deemphasis = 2 70 75 80 s fm_deemphasis = 1 45 50 54 s audio output load resistance 6,10 r l single-ended 10 ? ? k ? audio output load capacitance 6,10 c l single-ended ? ? 50 pf seek/tune time 6 rclk tolerance =100ppm ? ? 60 ms/channel powerup time 6 from powerdown ? ? 110 ms rssi offset 14 input levels of 8 and 60 dbv at rf input ?3 ? 3 db table 9. fm receiver characteristics 1,2 (continued) (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit notes: 1. additional testing information is available in applicati on note, ?an388: si470x/1x/2x/3 x/4x evaluation board test procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines? silicon laboratories will evaluate schematics and layo uts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. guaranteed by characterization. 7. v emf =1 mv. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 9. ? f = 75 khz. 10. at l out and r out pins. 11. analog audio output mode. 12. blocker amplitude = 100 dbv 13. sensitivity measured at (s+n)/n = 26 db. 14. at temperature 25c. free datasheet http:///
si4704/05-c40 14 rev. 1.0 table 10. 64?75.9 mhz input frequency fm receiver characteristics 1,2,6 (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 64 ? 75.9 mhz sensitivity with headphone network 3,4,5 (s+n)/n = 26 db ? 4.0 ? v emf lna input resistance 7 345k ? lna input capacitance 7 456pf input ip3 8 100 105 ? dbv emf am suppression 3,4,7 m = 0.3 40 50 ? db adjacent channel selectivity 200 khz ? 50 ? db alternate channel selectivity 400 khz ? 70 ? db audio output voltage 3,4,7 72 80 90 mv rms audio output l/r imbalance 3,7,9 ?? 1 db audio frequency response low ?3 db ? ? 30 hz audio frequency response high ?3 db 15 ? ? khz audio mono s/n 3,4,5,7,10 55 63 ? db audio thd 3,7,9 ?0.10.5 % de-emphasis time constant fm_deemphasis = 2 70 75 80 s fm_deemphasis = 1 45 50 54 s audio output load resistance 10 r l single-ended 10 ? ? k ? audio output load capacitance 10 c l single-ended ? ? 50 pf seek/tune time rclk tolerance =100ppm ? ? 60 ms/channel powerup time from powerdown ? ? 110 ms rssi offset 11 input levels of 8 and 60 dbv emf ?3 ? 3 db notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n board test procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines.? silico n laboratories will evaluate schematics and layouts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. guaranteed by characterization. 7. v emf =1 mv. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 9. ? f = 75 khz. 10. at l out and r out pins. 11. at temperature (25 c). free datasheet http:///
si4704/05-c40 rev. 1.0 15 table 11. reference clock and crystal characteristics (v dd = 2.7 to 5.5 v, v io = 1.85 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit reference clock rclk supported frequencies 1 31.130 32.768 40,000 khz rclk frequency tolerance 2 ?100 ? 100 ppm refclk_prescale 1 ? 4095 refclk 31.130 32.768 34.406 khz crystal oscillator crystal oscillator frequency ? 32.768 ? khz crystal frequency tolerance 2 ?100 ? 100 ppm board capacitance ? ? 3.5 pf notes: 1. the si4704/05 divides the rclk input by refclk_prescale to obtain refclk. there are some rclk frequencies between 31.130 khz and 40 mhz that are not supp orted. see ?an332: si47xx programming guide,? table 6 for more details. 2. a frequency tolerance of 50 ppm is required for fm seek/tune using 50 khz channel spacing. free datasheet http:///
si4704/05-c40 16 rev. 1.0 2. typical application schematic notes: 1. place c1 close to v dd pin. 2. all grounds connect directly to gnd plane on pcb. 3. pins 1 and 20 are no connects, leave floating. 4. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout, and design guidelines? silicon laboratories will evaluate schematics and layout s for qualified customers. 5. pin 2 or pin 4 connects to the fm antenna interface. pin 2 is for a headphone antenna. pin 4 is for an integrated antenna. 6. place si4704/05 as close as possible to antenna and keep the fmi and lpi traces as short as possible. optional: digital audio output 20 19 18 17 16 u1 si4704/05 sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 lout rout vbattery 2.7 to 5.5 v gpo1 gpo2/int gpo3/dclk vio 1.85 to 3.6 v fmi c2 c3 x1 rclk gpo3 optional: for crystal oscillator option dout lout rout gnd vdd nc gpo1 gpo2/int gpo3/dclk dfs nc fmi rfgnd lpi rst sen sclk sdio rclk vio dfs r1 r2 r3 dout lpi free datasheet http:///
si4704/05-c40 rev. 1.0 17 3. bill of materials component(s) value/description supplier c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata u1 si4704/05 fm radio re ceiver silicon laboratories optional components c2, c3 crystal load capacitors, 22 pf, 5%, cog (optional: for crystal oscillator option) venkel x1 32.768 khz crystal (optional: fo r crystal oscillator option) epson r1 resistor, 2 k ?? (optional: for digital audio) venkel r2 resistor, 2 k ?? (optional: for digital audio) venkel r3 resistor, 600 ?? (optional: for digital audio) venkel free datasheet http:///
si4704/05-c40 18 rev. 1.0 4. functional description 4.1. overview figure 9. functional block diagram the si4704/05 devic e leverages silicon laboratories? highly successful and pr oven si4700/01/02/03 fm receiver, and offers unmatched integration and performance. the si4704/05 offers additional features, such as en55020 compliance, embedded antenna support, and a digital audio interface. the si4704/05 is layout compatible with s ilicon laborator ies? si4710/11 fm transmitter, si4720/21 fm transceiver, and si4730/31 am/fm receiver. the si4704/05 is the first fm radio receiver integrated circuit to support a short pcb trace or wire antenna, which can be integrated into the enclosure or pcb. the si4704/05?s digital integration reduces the required external components of traditional offerings, resulting in a solution requiring only an external inductor and bypass capacitor, and occupying board space of approximately 15 mm 2 . other advantages of the si4704/05 include highly reliable device manufacturing, excellent quality, and ease of use to design-in and program. the si4704/05 includes line outputs from the on-chip digital-to-analog converters (dac), digital audio mixers, a programmable reference clock input, and a configurable digital audio in terface with the si4705. the chip supports an i 2 c-compliant 2-wire interface, an si4700/01/02/03 backwards compatible 3-wire control interface, and an spi control interface. the si4704/05 performs much of the fm demodulation digitally to achieve high fidelity, optimal performance versus power consumption, an d flexibility of design. the on-board dsp provides unmatched pilot rejection, selectivity, and optimum sound quality. the si4704/05 offers both the manufacturer and the end-user unmatched programmability and flexibility in the listening experience. the si4705 incorporates on- board processing capability for the european radio data system (rds) and the us radio broadcast data system (rbds) including all the symbol encoding/decoding, bl ock synchronization, error detection, and error correction functions. rds allows digital information sent from the broadcaster to be displayed, such as station id, song name, and music category. in europe, alternate frequency (af) information is also provided to automatically change stations in areas where broadcasters use multiple frequencies. the si4704/05 has two separate rf inputs. fmi is the input for use with a traditional fm antenna. the lpi input is for use with a short pcb trace or wire antenna that may be integrated into the system enclosure. there is a clocking mode to choose to clock the si4704/05 from a reference clock or crystal. on the si4705, there is an audio output mode to choose between an analog and/or digital audio output. adc adc si4704/05 dsp dac dac rout lout afc digital interface (si4705) gpo rfgnd lna fmi agc pga rclk reg vdd 2.7?5.5 v fm antenna xtal osc lpi 32.768 khz 0/90 dout dclk dfs vio 1.85-3.6 v sclk sdio control interface sen rssi rst rds (si4705) free datasheet http:///
si4704/05-c40 rev. 1.0 19 in the analog audio output mode, pin 13 is rout, pin 14 is lout, and pin 17 is gpo3. in the digital audio mode, pin 15 is dout, pin 16 is dfs, and pin 17 is dclk. concurrent analog/digital audio output mode requires pins 13, 14, 15, 16, and 17. the digital audio interface operates in slave mode and supports a variety of msb-first audio data formats including i 2 s and left-justified modes. the interface has three pins: digital data input (din), digital frame synchronization input (dfs), and a digital bit synchronization input clock (dclk). the si4704/05 supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 khz. the digital audio interface enables low-power operation by eliminating the need for redundant dacs and adcs on the audio baseband processor. the si4704/05 is reset by applying a logic low on rst signal. this causes all register values to be reset to their default values. the digital output interface supply (v io ) provides voltage to the rst , sen , sdio, rclk, dout, dfs, and dclk pins and can be connected to the audio baseband processor's supply voltage to save power and remove the need for volta ge level translators. rclk is not required for register operation. the si4704/05 reference clock is programmable, supporting many rclk inputs as shown in table 11. 4.2. application sche matics and operating modes the application schematic for the si4704/05 is shown in section "2. typical application schematic" on page 16. the si4704/05 supports selectable analog, digital, or concurrent analog and digital audio output modes. in the analog output mode, pin 13 is rout, pin 14 is lout, and pin 17 is gpo3. in the digital output mode, pin 15 is dout, pin 16 is dfs, and pin 17 is dclk. concurrent analog and digital audio output mode requires pins 13, 14, 15, 16, and 17. in addition to output mode, there is a clocking mode to clock the si4704/05 from a reference clock or crystal oscillator. the user sets the operating modes with commands as described in section "5. commands and properties" on page 25. 4.3. fm receiver the si4704/05 fm receiver is based on the proven si4700/01 fm tuner. the receiver uses a digital low-if architecture allowing the elimination of external components and factory adjustments. the si4704/05 integrates a low noise amplifier (lna) supporting the worldwide fm broadcast band (64 to 108 mhz). an agc circuit controls the gain of the lna to optimize sensitivity and rejection of strong interferers. an image- reject mixer downconverts the rf signal to low-if. the quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (adcs). this ad vanced architecture allows the si4704/05 to perform channel selection, fm demodulation, and stereo audio processing to achieve superior performance compared to traditional analog architectures. 4.4. digital audio interface (si4705 only) the digital audio interface operates in slave mode and supports three different audio data formats: ? i 2 s ? left-justified ? dsp mode 4.4.1. audio data formats in i 2 s mode, by default the msb is captured on the second rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is low, and the right channel is transferred when the dfs is high. in left-justified mode, by default the msb is captured on the first rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is high, and the right channel is transferred when the dfs is low. in dsp mode, the dfs becomes a pulse with a width of 1dclk period. the left channel is transferred first, followed right away by the right channel. there are two options in transferring the digital audio data in dsp mode: the msb of the left channel can be transferred on the first rising edge of dclk following the dfs pulse or on the second rising edge. in all audio formats, depending on the word size, dclk frequency, and sample rates, there may be unused dclk cycles after the lsb of each word before the next dfs transition and msb of the next word. in addition, if preferred, the user can configure the msb to be captured on the falling edge of dclk via properties. the number of audio bits can be configured for 8, 16, 20, or 24 bits. 4.4.2. audio sample rates the device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 khz. the digital audio interface enables low-power operation by eliminating the need for redundant dacs on the audio baseband processor. free datasheet http:///
si4704/05-c40 20 rev. 1.0 figure 10. i 2 s digital audio format figure 11. left-justified digital audio format figure 12. dsp digital audio format left channel right channel 1 dclk 1 dclk 13 2n n-1 n-2 13 2n n-1 n-2 lsb msb lsb msb dclk dout dfs inverted dclk (ofall = 1) (ofall = 0) i 2 s (omode = 0000) left channel right channel 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb dclk dout dfs inverted dclk (ofall = 1) (ofall = 0) left-justified (omode = 0110) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb dclk dout (msb at 1 st rising edge) dfs 13 2 left channel right channel 1 dclk (ofall = 0) (omode = 1100) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb 13 2 left channel right channel dout (msb at 2 nd rising edge) (omode = 1000) free datasheet http:///
si4704/05-c40 rev. 1.0 21 4.5. stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. the mpx standard was developed in 1961, and is used worldwide. today's mpx signal format consists of left + right (l+r) audio, left ? right (l?r) audio, a 19 khz pilot tone, and rds/rbds data as shown in figure 13 below. figure 13. mpx signal spectrum 4.5.1. stereo decoder the si4704/05's integrated stereo decoder automatically decodes the mpx signal using dsp techniques. the 0 to 15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l?r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l?r) signal. output left and right channels are obtained by adding and subtracting the (l+r) and (l?r) signals respectively. the si4705 uses frequency information from the 19 khz stereo pilot to recover the 57 khz rds/rbds signal. 4.5.2. stereo-mono blending adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. stereo/mono status can be monitored with the fm_rsq_status command. mono operation can be forced with the fm_blend_mono_threshold property. 4.6. de-emphasis pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high-frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. the si4704/05 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. two time constants are used in various regions. the de- emphasis time constant is programmable to 50 or 75 s and is set by the fm_deemphasis property. 4.7. stereo dac high-fidelity stereo digital-to-analog converters (dacs) drive analog audio signals onto the lout and rout pins. the audio output may be muted. volume is adjusted digitally with the rx_volume property. 4.8. soft mute the soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. the softmute attenuation level is adjustable using the fm_soft_mute_max_attenuation property. 4.9. rds/rbds processor (si4705 only) the si4705 implements an rds/rbds* processor for symbol decoding, block synchronization, error detection, and error correction. the si4705 device is user c onfigurable and provides an optional interrupt when rds is synchronized, loses synchronization, and/or the user configurable rds fifo threshold has been met. the si4705 reports rds decoder synchronization status and detailed bit errors in the information word for each rds block with the fm_rds_status command. the range of reportable block errors is 0, 1?2, 3?5, or 6+. more than six erro rs indicates that the corresponding block information word contains six or more non-correctable errors or that the block checkword contains errors. *note: rds/rbds is referred to only as rds throughout the remainder of this document. 057 53 38 23 19 15 frequency (khz) modulation level stereo audio left - right rds/ rbds mono audio left + right stereo pilot free datasheet http:///
si4704/05-c40 22 rev. 1.0 4.10. tuning the tuning frequency can be directly programmed using the fm_tune_freq command. the si4704/05 supports channel spacing steps of 10 khz in fm mode. 4.11. seek seek tuning will search up or down for a valid channel. valid channels are found when the receive signal strength indicator (rssi) and the signal-to-noise ratio (snr) values exceed the set threshold. using the snr qualifier rather than sole ly relying on the more traditional rssi qualifier can reduce false stops and increase the number of valid stations detected. seek is initiated using the fm_ seek_start command. the rssi and snr threshold settings are adjustable using properties (see table 14). 4.12. reference clock the si4704/05 reference clock is programmable, supporting rclk frequencies in table 11. refer to table 3, ?dc characteristics,? on page 5 for switching voltage levels and table 9, ?fm receiver characteristics,? on page 12 for frequency tolerance information. an onboard crystal oscillator is available to generate the 32.768 khz reference when an external crystal and load capacitors are provided. refer to "2. typical application schematic" on page 16. this mode is enabled using the power_up command. refer to table 13, ?selected si4704/05 commands,? on page 25. the si4704/05 performance may be affected by data activity on the sdio bus when using the integrated internal oscillator. sdio acti vity results from polling the tuner for status or communicating with other devices that share the sdio bus. if there is sdio bus activity while the si4704/05 is performing the seek/tune function, the crystal oscillator may experience jitter, which may result in mistunes, false stops, and/or lower snr. for best seek/tune resu lts, silicon laboratories recommends that all sdio data traffic be suspended during si4704/05 seek and tune operations. this is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. the seek/tune complete (stc) interrupt should be used instead of polling to determine when a seek/tune operation is complete. 4.13. control interface a serial port slave interface is provided, which allows an external controller to send commands to the si4704/05 and receive responses from the device. the serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or spi mode. the si4704/05 selects the bus mode by sampling the state of the gpo1 and gpo2 pins on the rising edge of rst . the gpo1 pin includes an internal pull-up resistor, which is connected while rst is low, and the gpo2 pin includes an internal pull- down resistor, which is connected while rst is low. therefore, it is only necessary for the user to actively drive pins which differ from these states. see table 12. after the rising edge of rst , the pins gpo1 and gpo2 are used as general purpose output (o) pins as described in section ?4.14. gpo outputs?. in any bus mode, commands may only be sent after v io and v dd supplies are applied. in any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (cts bit is high). 4.13.1. 2-wire cont rol interface mode when selecting 2-wire mode, the user must ensure that sclk is high during the rising edge of rst , and stays high until after the first start condition. also, a start condition must not occur within 300 ns before the rising edge of rst . the 2-wire bus mode uses only the sclk and sdio pins for signaling. a transa ction begins with the start condition, which occurs when sdio falls while sclk is high. next, the user drives an 8-bit control word serially on sdio, which is captured by the device on rising edges of sclk. the control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). the si4704/05 acknowledges the control word by driving sdio low on the next fa lling edge of sclk. table 12. bus mode select on rising edge of rst bus mode gpo1 gpo2 2-wire 1 0 spi 1 1 (must drive) 3-wire 0 (must drive) 0 free datasheet http:///
si4704/05-c40 rev. 1.0 23 although the si4704/05 will respond to only a single device address, this address can be changed with the sen pin (note that the sen pin is not used for signaling in 2-wire mode). when sen = 0, the 7-bit device address is 0010001b. when sen = 1, the address is 1100011b. for write operations, the user then sends an 8-bit data byte on sdio, which is captured by the device on rising edges of sclk. the si4704/05 acknowledges each data byte by driving sdio low for one cycle, on the next falling edge of sclk. the us er may write up to 8 data bytes in a single 2-wire transaction. the first byte is a command, and the next seven bytes are arguments. for read operations, after the si4704/05 has acknowledged the control byte, it will drive an 8-bit data byte on sdio, changing the state of sdio on the falling edge of sclk. the user acknowledges each data byte by driving sdio low for o ne cycle, on the next falling edge of sclk. if a data byte is not acknowledged, the transaction will end. the user may read up to 16 data bytes in a single 2-wire transaction. these bytes contain the response data from the si4704/05. a 2-wire transaction ends with the stop condition, which occurs when sdio rise s while sclk is high. for details on timing specifications and diagrams, refer to table 5, ?2-wire control interface characteristics? on page 7; figure 2, ?2-wire control interface read and write timing parameters,? on page 8, and figure 3, ?2- wire control interface read and write timing diagram,? on page 8. 4.13.2. 3-wire cont rol interface mode when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . the 3-wire bus mode uses the sclk, sdio, and sen _ pins. a transaction begins when the user drives sen low. next, the user drives a 9-bit control word on sdio, which is captured by th e device on rising edges of sclk. the control word consists of a 3-bit device address (a7:a5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (a4:a0). for write operations, the cont rol word is followed by a 16-bit data word, which is captured by the device on rising edges of sclk. for read operations, the cont rol word is followed by a delay of one-half sclk cycl e for bus turn-around. next, the si4704/05 will drive th e 16-bit read data word serially on sdio, changing the state of sdio on each rising edge of sclk. a transaction ends when the user sets sen high, then pulses sclk high and low one final time. sclk may either stop or continue to toggle while sen is high. in 3-wire mode, commands are sent by first writing each argument to register(s) 0xa1?0xa3, then writing the command word to register 0xa0. a response is retrieved by reading registers 0xa8?0xaf. for details on timing specific ations and diagrams, refer to table 6, ?3-wire control in terface characteristics,? on page 9; figure 4, ?3-wire control interface write timing parameters,? on page 9, and figure 5, ?3-wire control interface read timing pa rameters,? on page 9. 4.13.3. spi control interface mode when selecting spi mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . spi bus mode uses the sclk, sdio, and sen pins for read/write operations. the system controller can choose to receive read data from the device on either sdio or gpo1. a transaction begins when the system controller drives sen = 0. the system controller then pulses sclk eight times, wh ile driving an 8-bit control byte serially on sdio. the device captures the data on rising edges of sclk. the control byte must have one of five values: ? 0x48 = write a command (controller drives 8 additional bytes on sdio). ? 0x80 = read a response (device drives one additional byte on sdio). ? 0xc0 = read a response (device drives 16 additional bytes on sdio). ? 0xa0 = read a response (device drives one additional byte on gpo1). ? 0xe0 = read a response (dev ice drives 16 additional bytes on gpo1). for write operations, the system controller must drive exactly eight data bytes (a command and seven arguments) on sdio after the control byte. the data is captured by the device on the rising edge of sclk. for read operations, the controller must read exactly 1 byte (status) after the cont rol byte or exactly 16 data bytes (status and resp1?resp15) after the control byte. the device changes the state of sdio (or gpo1, if specified) on the falling ed ge of sclk. data must be captured by the system controller on the rising edge of sclk. free datasheet http:///
si4704/05-c40 24 rev. 1.0 keep sen low until all bytes have transferred. a transaction may be aborted at any time by setting sen high and toggling sclk high and then low. commands will be ignored by the devic e if the transaction is aborted. for details on timing specifications and diagrams, refer to figure 6 and figure 7 on page 10. 4.14. gpo outputs the si4704/05 provides three general-purpose output pins. the gpo pins can be configured to output a constant low, constant high, or high-impedance. the gpo pins can be reconfigur ed as specialized functions. gpo2/int can be configured to provide interrupts and gpo3 can be configured to provide external crystal support or as dclk in digital audio output mode. 4.15. reset, powerup, and powerdown setting the rst pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. setting the rst pin high will bring the device out of reset. a powerdown mode is available to reduce power consumption when the part is idle. putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 4.16. programmi ng with commands to ease development time and offer maximum customization, the si4704/0 5 provides a simple yet powerful software interface to program the receiver. the device is programmed using commands, arguments, properties, and responses. to perform an action, the user writes a command byte and associated arguments, causing the chip to execute the given command. commands control an action such as powerup the device, shut down the device, or tune to a station. arguments are specific to a given command and are used to modify the command. a partial list of commands is available in t able 13, ?selected si4704/05 commands,? on page 25. properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. examples of properties are de-emphasis level, rssi seek threshold, and soft mute attenuation threshold. a partial list of properties is available in table 14, ?selected si4704/05 properties,? on page 26. responses provide the user information and are echoed after a command and associated arguments are issued. all commands provide a one-byte status update indicating interrupt and clear-to-send status information. for a detailed description of the commands and properties for the si4704/05, see ?an332: universal programming guide.? free datasheet http:///
si4704/05-c40 rev. 1.0 25 5. commands and properties table 13. selected si4704/05 commands cmd name description 0x01 power_up powerup device and mode selection. modes include analog or digital output and reference clock or crystal support. 0x10 get_rev returns revision information on the device. 0x11 power_down powerdown device. 0x12 set_property sets the value of a property. 0x13 get_property retrieves a property?s value. 0x20 fm_tune_freq selects the fm tuning frequency. 0x21 fm_seek_start begins sear ching for a va lid frequency. 0x22 fm_tune_status queries the status of previous fm_tune_freq or fm_seek_start command. 0x23 fm_rsq_status queries the status of the received signal quality (rsq) of the current channel (si4705 only). 0x24 fm_rds_status returns rds information for current channel and reads an entry from the rds fifo (si4705 only). free datasheet http:///
si4704/05-c40 26 rev. 1.0 table 14. selected si4704/05 properties prop name description default 0x1100 fm_deemphasis sets deemphasis time constant. default is 75 us. 0x0002 0x1105 fm_blend_stereo_ threshold sets rssi threshold for stereo blend (full stereo above threshold, blend below threshold). to force stereo set this to 0. to force mono set this to 127. default value is 49 dbuv. 0x0031 0x1106 fm_blend_mono_ threshold sets rssi threshold for mono blend (full mono below threshold, blend above threshold). to force stereo set this to 0. to force mono set this to 127. default value is 30 dbuv. 0x001e 0x1200 fm_rsq_int_ source configures interrupt re lated to received signa l quality metrics. 0x0000 0x1302 fm_soft_mute_ max_attenuation sets maximum attenuation during soft mute (db). set to 0 to disable soft mute. default is 16 db. 0x0010 0x1400 fm_seek_band_ bottom sets the bottom of the fm band for seek. default is 8750. 0x222e 0x1401 fm_seek_band_top sets the top of the fm band for seek. defa ult is 10790. 0x2a26 0x1402 fm_seek_freq_ spacing selects frequency spacing for fm seek. 0x000a 0x1403 fm_seek_tune_ snr_threshold sets the snr threshold for a valid fm seek/tune. default value is 3 db. 0x0003 0x1404 fm_seek_tune_ rssi_treshold sets the rssi threshold for a valid fm seek/tune. default value is 20 dbuv. 0x0014 0x1500 rds_int_source configures rds interrupt behavior. 0x0000 0x1501 rds_int_fifo_count sets the minimum number of rds groups stored in the receive rds fifo required befo re rds recv is set. 0x0000 0x1502 rds_config configures rds setting. 0x0000 0x4000 rx_volume sets the output volume. 0x003f 0x4001 rx_hard_mute mutes the audio output. l and r audio outputs may be muted independently in fm mode. 0x0000 free datasheet http:///
si4704/05-c40 rev. 1.0 27 6. pin descriptions: si4704/05-gm pin number(s) name description 1, 20 nc no connect. leave floating. 2 fmi fm rf input. 3 rfgnd rf ground. connect to ground plane on pcb. 4 lpi loop antenna rf input. 5 rst device reset input (active low). 6 sen serial enable input (active low). 7 sclk serial clock input. 8 sdio serial data input/output. 9 rclk external reference or crystal oscillator input. 10 v io i/o supply voltage. 11 v dd supply voltage. may be connected directly to battery. 12, gnd pad gnd ground. connect to ground plane on pcb. 13 rout right audio analog line output. 14 lout left audio analog line output. 15 dout digital audio output data. 16 dfs digital frame synchronization. 17 gpo3/dclk general purpose out put/digital bit synchronous clock or crystal oscillator input. 18 gpo2/int general purpose output/interrupt. 19 gpo1 general purpose output. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio dout lout rout gnd rst nc lpi rclk sdio vdd fmi rfgnd gpo3/dclk nc gpo1 dfs sclk sen free datasheet http:///
si4704/05-c40 28 rev. 1.0 7. ordering guide part number* description package type operating temperature SI4704-C40-gm fm broadcast radio receiver qfn pb-free ?20 to 85 c si4705-c40-gm fm broadcast radio receiver with rds/rbds qfn pb-free ?20 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel. free datasheet http:///
si4704/05-c40 rev. 1.0 29 8. package markings (top marks) 8.1. si4704 top mark figure 14. si4704 top mark 8.2. si4705 top mark figure 15. si4705 top mark 8.3. top mark explanation mark method: yag laser line 1 marking: part number 04 = si4704 05 = si4705 firmware revision 40 = firmware revision 4.0 line 2 marking: r = die revision c = revision c die. ttt = internal code internal tracking code. line 3 marking: circle = 0.5 mm diameter (bottom-left justified) pin 1 identifier. y = year ww = workweek assigned by the assembly hous e. corresponds to the last significant digit of the year and workweek of the mold date. 0440 cttt yww 0540 cttt yww free datasheet http:///
si4704/05-c40 30 rev. 1.0 9. package outl ine: si4704/05-gm figure 16 illustrates the package details for the si4704/05. table 1 5 lists the values for the dimensio ns shown in the illustration. figure 16. 20-pin quad flat no-lead (qfn) table 15. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.50 0.55 0.60 f 2.53 bsc a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.200.250.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. free datasheet http:///
si4704/05-c40 rev. 1.0 31 10. pcb land pattern: si4704/05-c40-gm figure 17 illustrates the pcb land pattern details for the si4704/05-gm. table 16 lists t he values for the dimensions shown in the illustration. figure 17. pcb land pattern free datasheet http:///
si4704/05-c40 32 rev. 1.0 table 16. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m- 1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut, and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is pe r the jedec/ipc j-std-020 specification for small body components. free datasheet http:///
si4704/05-c40 rev. 1.0 33 11. additional reference resources contact your local sales representative s for more information or to obtain copies of the following references: ? en55020 compliance test certificate ? an332: si47xx programming guide ? an383: si47xx antenna, schematic, layout, and design guidelines ? an388: si470x/1x/2x/3x/4x eval uation board test procedure free datasheet http:///
si4704/05-c40 34 rev. 1.0 d ocument c hange l ist revision 0.7 to revision 0.71 ? v io minimum changed from 1.5 v to 1.85 v. revision 0.71 to revision 1.0 ? updated patent information on page 1. ? updated table 3 on page 5. free datasheet http:///
si4704/05-c40 rev. 1.0 35 n otes : free datasheet http:///
si4704/05-c40 36 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. free datasheet http:///

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